### 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|ECE1192

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• Statistical Inference 统计推断
• Statistical Computing 统计计算
• Advanced Probability Theory 高等楖率论
• Advanced Mathematical Statistics 高等数理统计学
• (Generalized) Linear Models 广义线性模型
• Statistical Machine Learning 统计机器学习
• Longitudinal Data Analysis 纵向数据分析
• Foundations of Data Science 数据科学基础

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|Design Issues of VLSI Circuits

A VLSI manufacturing process is called a submicron $(\mathrm{SM})$ process when the feature size is below $1 \mu \mathrm{m}$, and a deep submicron (DSM) process when the feature size is roughly below $0.25 \mu \mathrm{m}^{2}$ The corresponding devices made by these two processes are denoted SM devices and DSM devices, respectively. At present, DSM devices are popular in the design of a large-scale system because they provide a more economical way to integrate a much more complicated system into a single chip. The resulting chip is often referred to as a system-on-a-chip (SoC) device.

Even though DSM processes allow us to design a very complicated large-scale system, many design challenges indeed exist, in particular, when the feature sizes are beyond $0.13 \mu \mathrm{m}$. The associated design issues can be subdivided into two main classes: DSM devices and DSM interconnect. ${ }^{3}$ In the following, we address each of these briefly.

The design issues of DSM devices include thin-oxide (gate-oxide) tunneling/breakdown, gate leakage current, subthreshold current, velocity saturation, short-channel effects on $V_{T}$, hot-carrier effects, and draininduced barrier lowering (DIBL) effect.

The device features of typical DSM processes are summarized in Table $1.1$. From the table, we can see that the thin-oxide (gate-oxide, i.e., silicon dioxide, $\mathrm{SiO}_{2}$ ) thickness is reduced from $5.7 \mathrm{~nm}$ in a $0.25-\mu \mathrm{m}$ process down to $1.65 \mathrm{~nm}$ in a $32-\mathrm{nm}$ process. The side effects of this reduction are thin-oxide tunneling and breakdown. The thin-oxide tunneling may cause an extra gate leakage current. To avoid thin-oxide breakdown, the operating voltage applied to the gate has to be lowered. This means that the noise margins are reduced accordingly and the subthreshold current may no longer be ignored. To reduce the gate leakage current, high- $k$ MOS transistors are widely employed starting from a $45-\mathrm{nm}$ process. In high- $k$ MOS transistors, a high- $k$ dielectric is used to replace the gate oxide. Hence, the gate-dielectric thickness may be increased significantly, thereby reducing the gate leakage current dramatically. The actual gatedielectric thickness depends on the relative permittivity of gate-dielectric material, referring to Section 3.4.1.2 for more details.

In addition, as the channel length of a device is reduced, velocity saturation, shortchannel effects on $V_{T}$, and hot-carrier effects may no longer be ignored as in the case of a long-channel device. The electron and hole velocities in the channel or silicon bulk is proportional to the applied electric field when the electric field is below a critical value. However, these velocities will saturate at a value of about $8 \times 10^{6} \mathrm{~cm} / \mathrm{sec}$ at 400 $\mathrm{K}$, which is independent of the doping level and corresponds to an electric field with the strength of $6 \times 10^{4} \mathrm{~V} / \mathrm{cm}$ for electrons and $2.4 \times 10^{5} \mathrm{~V} / \mathrm{cm}$ for holes, respectively. When velocity saturation happens, the drain current of a MOS transistor will follow a linear rather than a quadratical relationship with applied gate-to-source voltage.

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|Economics of VLSI

The cost of an IC is roughly composed of two major factors: fixed cost and variable cost. The fixed cost, also referred to as the nonrecurring engineering (NRE) cost, is independent of the sales volume. It is mainly contributed by the cost from that a project is started until the first successful prototype is obtained. More precisely, the fixed cost covers direct and indirect costs. The direct cost includes the research and design (R\&D) cost, manufacturing mask cost, as well as marketing and sales cost; the indirect cost comprises the investment of manufacturing equipments, the investment of CAD tools, building infrastructure cost, and so on. The variable cost is proportional to the product volume and is mainly the cost of manufacturing wafers, namely, wafer price, which is roughly in the range between 1,200 and 1,600 USD for a 300 -mm wafer.

From the above discussion, the cost per IC can be expressed as follows.
Cost per $\mathrm{IC}=$ Variable cost of $\mathrm{IC}+\frac{\text { Fixed cost }}{\text { Volume }}$
The variable cost per IC can be formulated as the following equation.
Variable cost of $\mathrm{IC}=$
Cost of die $+$ Cost of testing die $+$ Cost of packaging and final test
Final test yield $\times$ Dies per wafer
The cost of a die is the wafer price divided by the number of good dies and can be represented as the following formula.
$$\text { Cost of die }=\frac{\text { Wafer price }}{\text { Dies per wafer } \times \text { Die yield }}$$
The number of dies in a wafer, excluding fragmented dies on the boundary, can be approximated by the following equation.
Dies per wafer $=\frac{3}{4} \frac{d^{2}}{A}-\frac{1}{2 \sqrt{A}} d$
where $d$ is the diameter of the wafer and $A$ is the area of square dies. The derivation of this equation is left to the reader as an exercise.
The die yield can be estimated by the following widely used function.
Die yield $=\left(1+\frac{D_{0} A}{\alpha}\right)^{-\alpha}$
where $D_{0}$ is the defect density, i.e., the defects per unit area, in defects $/ \mathrm{cm}^{2}$, and $\alpha$ is a measure of manufacturing complexity. The typical values of $D_{0}$ and $\alpha$ are $0.3$ to $1.3$ and $4.0$, respectively. From this equation, it is clear that the die yield is inversely proportional to the die area.

The following two examples exemplify the above concepts about the cost of an IC. In these two examples, we intend to ignore the fixed cost and only take into account the wafer price when calculating die cost.

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|Design Issues of VLSI Circuits

DSM 器件的设计问题包括薄氧化物 (gate-oxide) 隧穿/击穿、栅极漏电流、亚阈值电流、速度饱和、在吨，热载流子效应和漏极降低势垒（DIBL）效应。

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|Economics of VLSI

$I C$ 的成本大致由两个主要因素组成：固定成本和可变成本。固定成本，也称为非经常性工程 (NRE) 成本，与销量无 关。它主要来自从项目启动到获得第一个成功原型的成本。更准确地说，固定成本包括直接成本和间接成本。直接 成本包括研究和设计 (RI\&D) 成本、制造掩模成本，以及营销和销售成本；间接成本包括制造设备投资、CAD工 具投资、基础设施建设成本等。可变成本与产品数量成正比，主要是制造晶圆的成本，即晶圆价格， 300 毫米晶圆 大致在1200-1600美元之间。

$$\text { Cost of die }=\frac{\text { Wafer price }}{\text { Dies per wafer } \times \text { Die yield }}$$

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